As for a chip design of the LSI, after a logic circuit design is performed in the upper process, a layout design is performed based on the data obtained by the logic circuit design. As a high integration of the LSI is advanced, since there is a limit on a manual design, an automatic design using a computer instead of the manual design is used. In recent years, an automatic design supporting development tool called EDA (Electronic Design Automatic) is used in the chip design by the computer.
In addition, IP (Intellectual Properties) is distributed for the purpose of shortening a design development period of the LSI. The IP is reusable data organized by a functional unit of a circuit block of the LSI and is provided to a chip designer by an IP provider. The IP is generally divided into software IP and hardware IP. Since the software IP is provided as function description data, the chip designer needs to determine a layout of the software IP and confirm manufacturing validity of it. In contrast, as for the hardware IP, while only a particular manufacturer can manufacture a chip using it, since the hardware IP is provided in a form including layout data and it is able to be manufactured and its behavior is ensured, there is such a merit that the design is easy, compared with the software IP.
By the way, since the hardware IP is provided in a form including layout data and netlist, confidential information including design know-how and circuit information of the hardware IP may be revealed to the chip designer. Therefore, it is considered that the data in the hardware IP which can be disclosed to the chip designer is provided to the chip designer as box IP. However, while the chip designer can perform the chip design itself in case of using the box IP, the chip designer may be unable to sufficiently perform data verifications such as a design pattern check. Therefore, it may cause a difference between a result of a data verification by the chip designer and a result of a data verification in case of using the hardware IP which is performed later by a chip manufacturer. In this case, since an operation returns to the chip design step, it causes a delay of the chip design development. Additionally, in such a case that the chip designer performs the layout design by setting an excessive margin for the purpose of preventing it, the size of the chip may become larger.